The present invention relates to a semiconductor integrated circuit having as its function the prevention of the destruction of a MOS transistor.
Erasable/programmable read only memories (EPROM) require an operating voltage of, e.g., 5 V and a writing voltage of, e.g., 20 V, which is higher than the operating voltage in the data program mode or data writing mode. In order to get the higher drain avalanche breakdown voltage of a MOS transistor to which a voltage of 20 V is applied, various procedures are employed.
FIG. 1 schematically shows a memory circuit including a floating gate type MOS transistor TR1 which constitutes a memory cell. One end of a current path of the MOS transistor TR1 is grounded and the other end is connected to a high voltage terminal VH through MOS transistors TR2 and TR3 in series. Row and column selection signals from row and column decoders (not shown) are supplied to gates of the MOS transistors TR1 and TR2, while a data signal is supplied to a gate of the MOS transistor TR3 in the writing mode. When writing data, the row and column selection signals, with a voltage level of VH (20 V), are supplied to the gates of the MOS transistors TR1 and TR2, and the data signal at the VH level is supplied to the gate of the MOS transistor TR3. However, when no data is being written in the MOS transistor TR1, a signal of 0 V is supplied to the gate of the MOS transistor TR3, thereby making the MOS transistor TR3 non-conductive.
It is generally known that MOS transistors have a lower drain avalanche breakdown voltage due to the electric field between the drain and the gate when a gate voltage of 0 V is applied than when a turn-on voltage is applied to the gate. On one hand, as the elements become small, the gate insulation film becomes thin, so that the electric field between the drain and the gate becomes strong and thus causes the breakdown voltage to be lowered.
To prevent such a reduction in the breakdown voltage, as shown in FIG. 2, the impurity concentration of the portion of the drain close to the gate is made lower than that of the residual portion, thereby weakening the electric field between the gate and the drain.
In FIG. 2, n.sup.+ -type regions 1 and 2 are formed to face each other in the surface area of a p-type substrate 3. An n.sup.- -type region 4 is formed so as to come into contact with the n.sup.+ -type region 2 and extend in the direction of the n.sup.+ -type region 1. A gate insulation film 5 is formed on the partial area of the p-type substrate 3 between the n.sup.+ -type region 1 and the n.sup.- -type region 4. A gate electrode 6 is further formed on the gate insulation film 5. The n.sup.+ -type region 1 forms the source and the n.sup.+ -type region 2 and n.sup.- -type region 4 cooperatively form the drain. A data signal is supplied to the gate electrode 6 and the n.sup.+ -type region 2 is connected to the high voltage terminal VH and the n.sup.+ -type region 1 is connected to, for example, a drain of the MOS transistor TR2.
In such an arrangement, when a high voltage is applied to the high voltage terminal VH, a wider depletion layer is formed between the n.sup.- -type region 4 and the substrate 3, so that the electric field between the n.sup.- -type region 4 and the gate electrode 6 becomes weak, thereby causing the breakdown voltage of this MOS transistor to be improved. However, if an abnormally high voltage is applied to the high voltage terminal VH due to the influence of static electricity or the like, a voltage higher than the dielectric breakdown voltage is applied to the gate insulation film 5 since the drain breakdown voltage is high, so that there is a possibility that this gate insulation film may be broken. This problem could easily occur as the elements become smaller and the gate insulation film becomes thinner.
Recently, a semiconductor integrated circuit having an output buffer circuit constructed by MOS transistors having similar structures as those shown in FIG. 2 has been provided. In operation, a voltage of 5 V is applied to drains of the MOS transistors of this output buffer circuit. However, when those drains are disconnected from a power source, an abnormally high voltage may be applied to the drains due to the influence of static electricity. In such a case, there is a possibility that the gate insulation films of the MOS transistors of the output buffer circuit will be broken as in the foregoing case.